Integrated radio frequency (RF) technologies require low resistance, low inductance, and low capacitance paths from active components to ground for proper operation. However, as the frequency of operation increases, the inductance of certain interconnection structures, such as bond wires, significantly limits performance. Conventional solutions include through wafer vias (TWVs) extending to a backside ground connection of the wafer. To reduce intrinsic device capacitances, high resistivity silicon substrates having resistances of greater than 10 Ω/cm, for example, may be used. However, the use of grounded TWVs and high resistivity substrates within the same integrated technology may result in inadequate isolation between the devices within the substrate and the TWVs. For example, a heavily doped planar junction biased at 20V with respect to a 500 Ω/cm P-type substrate will result in a depletion region around the junction having a width of approximately 30 μm. Further increasing the bias voltage or the resistivity of the substrate will increase the width of this depletion region. If the TWV is located within this depletion region, the TWV will provide a source of carriers and recombination centers, resulting in excessive leakage current between the devices and the TWV.
To isolate the depletion region around the TWV, conventional solutions have utilized PN junction isolation. However, junction isolation requires the addition of a costly lithography step and long diffusion thermal cycles, which may not be compatible with the rest of the process sequence. In addition, diffusion of dopants from the junction may compromise the effectiveness of the high resistivity substrate unless very wide exclusion zones are maintained around the TWV.